Flip-flops are commonly used in digital circuits for holding data. Conventionally, data are captured in flip-flops, for example, at the rising edge of the system clock. For reliable performance, the data must be received by flip-flops before the system clock comes in with a margin known as setup constraint. After the arrival of the system clock, the data must be maintained for a duration known as hold constraint. If the actual setup time is less than the setup constraint, a setup violation occurs. Similarly, if the actual hold time is less than the hold constraint, a hold violation occurs. The setup and hold violation problems need to be solved before the manufacturing of the respective integrated circuits.
Conventionally, the hold violation problem may be solved by inserting buffer(s) into the data path. By inserting the buffer(s) into the data path of a flip-flop, the arrival time of the data to flip-flops behind the inserted buffer(s) may be delayed, so that the hold time may be greater than the hold constraint. The delaying of the data may also be achieved by gate sizing or detour routings. However, these methods result in problems such as increased power, increased chip area usage, and setup issues such as increased noise-induced delay.
Another method for fixing the hold violation problem is to adjust clock skewing, so that the system clock may arrive earlier, which may also increase the actual hold time to greater than the hold constraint. However, this may have ripple effects to other parts of a respective clock tree, and new hold violations may be generated in other parts of the integrated circuit. Further, timing closure iterations may be needed to solve any newly generated violations. This significantly increases the design cycle time and cost.